Icarus Verilog - Revision history

Weibullguy at 18:24, 18 August 2008

2008-08-18T18:24:58Z

← Older revision		Revision as of 18:24, 18 August 2008
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	\|Tool to simplify the compilation of VPI modules for use with Icarus Verilog.		\|Tool to simplify the compilation of VPI modules for use with Icarus Verilog.
	\|}		\|}

			[[Category:Science_Engineering]]

Weibullguy: Multilibbed it

2007-09-15T20:07:34Z

Multilibbed it

← Older revision		Revision as of 20:07, 15 September 2007
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	Compile the package:		Compile the package:

	./configure --prefix=/usr &&		./configure --prefix=/usr &&
	make		make
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	=== 32Bit ===		=== 32Bit ===

	~~To do ..~~.		Compile the package:

			CC="gcc ${BUILD32}" CXX="gcc ${BUILD32}" PKG_CONFIG_PATH=${PKG_CONFIG_PATH32}" \
			./configure --prefix=/usr &&
			make

			Install the package
			make install

	=== N32 ===		=== N32 ===

	~~To do ..~~.		Compile the package:

			CC="gcc ${BUILDN32}" CXX="gcc ${BUILDN32}" PKG_CONFIG_PATH=${PKG_CONFIG_PATHN32}" \
			./configure --prefix=/usr --libdir=/usr/lib32 &&
			make

			Install the package
			make install

	=== 64Bit ===		=== 64Bit ===

	~~To do ..~~.		Compile the package:

			CC="gcc ${BUILD64}" CXX="gcc ${BUILD64}" PKG_CONFIG_PATH=${PKG_CONFIG_PATH64}" \
			./configure --prefix=/usr --libdir=/usr/lib64 &&
			make

			Install the package
			make install

			Install the example files:
			install -v -m755 -d /usr/share/doc/verilog/examples &&
			cp -v examples/* /usr/share/doc/verilog/examples

	== Contents ==		== Contents ==

Weibullguy at 20:53, 16 April 2007

2007-04-16T20:53:51Z

← Older revision		Revision as of 20:53, 16 April 2007
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	\|}		\|}

	~~== Introduction to Icarus Verilog ==~~		----
	Icarus Verilog is a a GPLed Verilog compiler. Icarus Verilog includes a a parser that parses Verilog (plus extensions) and generates an internal netlist. The netlist is passed to various processing steps that transform the design to more optimal/practical forms, then passed to a code generator for final output. The processing steps and the code generator are selected by command line switches.

	~~<b>Homepage:<~~/b> http://www.icarus.com/eda/verilog		{{Package-Introduction\|Icarus Verilog is a a GPLed Verilog compiler. Icarus Verilog includes a a parser that parses Verilog (plus extensions) and generates an internal netlist. The netlist is passed to various processing steps that transform the design to more optimal/practical forms, then passed to a code generator for final output. The processing steps and the code generator are selected by command line switches.\|http://www.icarus.com/eda/verilog}}

	== Dependencies ==		== Dependencies ==

Chipster19 at 16:02, 21 March 2007

2007-03-21T16:02:38Z

← Older revision		Revision as of 16:02, 21 March 2007
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	== Dependencies ==		== Dependencies ==

	=== ~~Optional~~ ===		=== Recommended ===
	* [[gperf]]		* [[gperf]]

Weibullguy: Created page.

2006-12-29T18:35:30Z

Created page.

New page

{| style="text-align: left; background-color: AliceBlue;"
|-
!Download Source:
|ftp://ftp.geda.seul.org/pub/geda/dist/verilog-{{Verilog-Version}}.tar.gz
|}

== Introduction to Icarus Verilog ==
Icarus Verilog is a a GPLed Verilog compiler. Icarus Verilog includes a a parser that parses Verilog (plus extensions) and generates an internal netlist. The netlist is passed to various processing steps that transform the design to more optimal/practical forms, then passed to a code generator for final output. The processing steps and the code generator are selected by command line switches.

<b>Homepage:</b> http://www.icarus.com/eda/verilog

== Dependencies ==

=== Optional ===
* [[gperf]]

== Non-Multilib ==

Compile the package:
./configure --prefix=/usr &&
make

Install the package
make install

Install the example files:
install -v -m755 -d /usr/share/doc/verilog/examples &&
cp -v examples/* /usr/share/doc/verilog/examples

== Multilib ==

=== 32Bit ===

To do ...

=== N32 ===

To do ...

=== 64Bit ===

To do ...

== Contents ==

{| style="text-align: left;"
|-valign="top"
!Installed Directories:
|/usr/lib/ivl
|-valign="top"
!Installed Programs:
|
iverilog, vvp, iverilog-vpi
|-valign="top"
!Installed Libraries:
|
libvpi.a, libveriuser.a
|}

=== Short Descriptions ===

{| style="text-align: left;"
|-valign="top"
!iverilog:
|Compiler that translates Verilog source code into executable programs for simulation, or other netlist formats for further processing.
|-valign="top"
!vvp:
|Run time engine that executes the default compiled form generated by Icarus Verilog.
|-valign="top"
!iverilog-vpi:
|Tool to simplify the compilation of VPI modules for use with Icarus Verilog.
|}